EEDG6331 - High-Level Synthesis: Design and Verification

EEDG 6331 (CE 6331) High-Level Synthesis: Design and Verification (3 semester credit hours) Facilitate the design of dedicated hardware using higher levels of abstraction (ANSI-C, C++ or SystemC) instead of hardware description languages like Verilog or VHDL. Theory of HLS process is comprehensively studied including: technology independent optimizations, resource allocation, scheduling, and binding stages. Students will design different types of hardware accelerators using HLS and learn how to design and verify complete hardware systems using only C. Course projects may include, but are not limited to: Building an automated HLS design space explorer, design of neural networks and building complete systems in C. Commercially available EDA tools will be used during the course. Prerequisite: EE 3320 or equivalent, C/C++. (3-0) Y