EEDG6370 - Design and Analysis of Reconfigurable Systems

EEDG 6370 (CE 6370) Design and Analysis of Reconfigurable Systems (3 semester credit hours) Introduction to reconfigurable computing. Review different programmable architectures. Software environments for reconfigurable systems and CAD flow, including High-level Synthesis (HLS), logic synthesis, technology mapping, and place and route. Emphasis on using ANSI-C, C++, or SystemC instead of Verilog or VHDL. Theory of HLS process including technology independent optimizations, resource allocation, scheduling, and binding stages. Use of FPGAs in applications including emulation, data centers, custom computing, and embedded application-based computing. Students will design different hardware accelerators using HLS and prototype them on an FPGA. Prerequisite: EE 3320 or equivalent. (3-0) R